In conventional graphics processing systems, an object to be displayed is typically represented as a set of one or more graphics primitives. Examples of graphics primitives include one-dimensional graphics primitives, such as lines, and two-dimensional graphics primitives, such as polygons. Typically, a graphics primitive is defined by a set of vertices each having a set of vertex attributes. For example, a graphics primitive can be a triangle that is defined by three different vertices, and each of the vertices can have up to 128 different vertex attributes, such as spatial coordinates, color components, fog components, normal vectors, specularity components, and texture coordinates.
Conventional graphics processing systems are typically implemented using a graphics pipeline having multiple pipeline stages. During operation of the graphics pipeline, one pipeline stage can perform a set of graphics processing operations on vertex attributes, and can then issue the vertex attributes for further processing by another pipeline stage. This seemingly straightforward routing of vertex attributes can quickly become complex if various pipeline stages have different processing requirements with respect to the vertex attributes. For example, one pipeline stage can operate on vertex attributes that are in one particular order, while another pipeline stage can operate on the vertex attributes that are in a different order. A further complication can occur if vertex attributes issued by one pipeline stage are stored in a memory, such as a Dynamic Random Access Memory (“DRAM”), pending retrieval of the vertex attributes for further processing by another pipeline stage. In particular, a DRAM typically permits memory access in increments of a particular byte size and for particular ranges of addresses. Unfortunately, vertex attributes as issued by a pipeline stage may not be arranged in a manner that is conducive to efficient memory access and, thus, can require an undesirable number of memory accesses for storage in the DRAM. As a result of these complications, it can be challenging to route vertex attributes while reducing congestion and achieving a desired level of throughput.
It is against this background that a need arose to develop the apparatus and method described herein.